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(R)
X9317
Low Noise, Low Power, 100 Taps
Data Sheet September 9, 2005 FN8183.1
Digitally Controlled Potentiometer (XDCPTM)
The Intersil X9317 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications.
Features
* Solid-State Potentiometer * 3-Wire Serial Up/Down Interface * 100 Wiper Tap Points - Wiper position stored in nonvolatile memory and recalled on power-up * 99 Resistive Elements - Temperature compensated - End to end resistance range 20% * Low Power CMOS - VCC = 2.7V to 5.5V, and 5V 10% - Standby current < 1A * High Reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years * RTOTAL Values = 1k, 10k, 50k, 100k * Packages - 8 Ld SOIC, DIP, TSSOP, and MSOP * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* LCD Bias Control * DC Bias Adjustment * Gain and Offset Trim * Laser Diode Bias Control * Voltage Regulator Output Control
Pinouts
X9317 (8 LD TSSOP) TOP VIEW X9317 (8 LD DIP, 8 LD SOIC, 8 LD MSOP) TOP VIEW
CS VCC INC U/D
1 2 3 4 X9317
8 7 6 5
RL/VL RW/VW VSS RH/VH
INC U/D RH VSS
1 2 3 4 X9317
8 7 6 5
VCC CS RL RW
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9317 Ordering Information
PART NUMBER X9317ZM8* X9317ZM8Z* (Note) X9317ZM8I* X9317ZM8IZ* (Note) X9317ZP X9317ZS8* X9317ZS8Z* (Note) X9317ZS8I* X9317ZS8IZ* (Note) X9317ZV8* X9317ZV8Z* (Note) X9317ZV8I* X9317ZV8IZ* (Note) X9317WM8* X9317WM8Z* (Note) X9317WM8I* X9317WM8IZ* (Note) X9317WP X9317WPI X9317WS8* X9317WS8Z* (Note) X9317WS8I* X9317WS8IZ* (Note) X9317WV8* X9317WV8Z* (Note) X9317WV8I* X9317WV8IZ* (Note) X9317UM8* X9317UM8Z* (Note) X9317UM8I* X9317UM8IZ* (Note) X9317UP X9317UPI X9317US X9317US8* X9317US8Z* (Note) X9317US8I* X9317US8IZ* (Note) X9317UV8* X9317UV8Z* (Note) X9317UV8I* X9317UV8IZ* (Note) X9317U X9317U Z X9317U I X9317U Z I 9317U 9317U Z 317UI 9317UI Z DDA AFI DCY X9317ZP X9317Z X9317Z Z X9317Z I X9317Z Z I 9317Z 9317Z Z 317ZI 9317ZI Z ABF DCW ADS DCT X9317WP X9317WP I X9317W X9317W Z X9317W I X9317W Z I 9317W 9317W Z 317WI 9317WI Z AEC DCS AFE DCR X9317UP X9317UP I 50 10 PART MARKING VCC LIMITS (V) 5 10% RTOTAL (k) 1 TEMPERATURE RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free)
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FN8183.1 September 9, 2005
X9317 Ordering Information (Continued)
PART NUMBER X9317TM8* X9317TM8Z* (Note) X9317TM8I* X9317TM8IZ* (Note) X9317TP X9317TPI X9317TS8 X9317TS8Z (Note) X9317TS8I X9317TS8IZ (Note) X9317TV8* X9317TV8Z* (Note) X9317TV8I* X9317TV8IZ* (Note) X9317ZM8-2.7* X9317ZM8Z-2.7* (Note) X9317ZM8I-2.7* X9317ZM8IZ-2.7* (Note) X9317ZS8-2.7* X9317ZS8Z-2.7* (Note) X9317ZS8I-2.7* X9317ZS8IZ-2.7* (Note) X9317ZV8-2.7* X9317ZV8Z-2.7* (Note) X9317ZV8I-2.7* X9317ZV8IZ-2.7* (Note) X9317WM8-2.7* X9317WM8Z-2.7* (Note) X9317WM8I-2.7* X9317WP-2.7 X9317WPI-2.7 X9317WS8-2.7* X9317WS8Z-2.7* (Note) X9317WS8I-2.7* X9317WS8IZ-2.7* (Note) X9317WV8-2.7* X9317WV8Z-2.7* (Note) X9317WV8I-2.7* X9317WV8IZ-2.7* (Note) 9317TI Z AFH AOA AFJ DCZ X9317Z F X9317Z Z F X9317Z G X9317Z Z G 317ZF 9317ZF Z 317ZG 317ZG Z ACZ DCX ADT X9317WP F X9317WP G X9317W F X9317W Z F X9317W G X9317W Z G 317WF 9317WF Z 317WG AKZ 10 2.7-5.5 1 9317T Z X9317TP I X9317T X9317T Z X9317T I X9317T Z I PART MARKING AGD DCN AGF DCL VCC LIMITS (V) RTOTAL (k) 100 TEMPERATURE RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free)
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FN8183.1 September 9, 2005
X9317 Ordering Information (Continued)
PART NUMBER X9317UM8-2.7* X9317UM8Z-2.7* (Note) X9317UM8I-2.7* X9317UM8IZ-2.7* (Note) X9317UP-2.7 X9317UPI-2.7 X9317US8-2.7* X9317US8Z-2.7* (Note) X9317US8I-2.7* X9317US8IZ-2.7* (Note) X9317UV8-2.7* X9317UV8Z-2.7* (Note) X9317UV8I-2.7* X9317UV8IZ-2.7* (Note) X9317TM8-2.7* X9317TM8Z-2.7* (Note) X9317TM8I-2.7* X9317TM8IZ-2.7* (Note) X9317TP-2.7 X9317TPI-2.7 X9317TS8-2.7* X9317TS8Z-2.7* (Note) X9317TS8I-2.7* X9317TS8IZ-2.7* (Note) X9317TV8-2.7* X9317TV8Z-2.7* (Note) X9317TV8I-2.7* X9317TV8IZ-2.7* (Note) 9317TF Z 317TG 9317TG Z X9317T Z F X9317T G X9317T Z G X9317TP G PART MARKING AED AOB AFF AOH X9317UP F X9317UP G X9317U F X9317U Z F X9317U G X9317U Z G 9317UF 9317UF Z 9317UG 9317UG Z AGE DCP AGG DCM 100 VCC LIMITS (V) RTOTAL (k) 50 TEMPERATURE RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free) 8 Ld TSSOP 8 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel.
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FN8183.1 September 9, 2005
X9317 Block Diagram
VCC (Supply Voltage) U/D INC CS Up/Down Counter 99 98 97 7-Bit Nonvolatile Memory 96 One of One Hundred Decoder 2 VSS (Ground) General Store and Recall Control Circuitry 1 0 RL RW Detailed RH
Up/Down (U/D) Increment (INC) Device Select (CS) Control and Memory
RH
RW
Wiper Switches
Resistor Array
RL
VCC VSS
Pin Descriptions
DIP/SOIC 1 2 3 4 5 6 7 8 SYMBOL INC U/D RH VSS RW RL CS VCC BRIEF DESCRIPTION Increment. Toggling INC while CS is low moves the wiper either up or down. Up/Down. The U/D input controls the direction of the wiper movement. The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. Ground. The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer. The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is high. Supply Voltage.
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FN8183.1 September 9, 2005
X9317
Absolute Maximum Ratings
Junction Temperature Under Bias . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D and VCC with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V RH, RW, RL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V Lead Temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8mA
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Potentiometer Specifications VCC = Full Range, TA = Full Operating Temperature Range unless otherwise stated
SYMBOL RTOTAL VRH/RL PARAMETER End to end resistance tolerance RH/RL terminal voltage Power rating TEST CONDITIONS/NOTES See ordering information for values VSS = 0V RTOTAL 10k RTOTAL = 1k RW Wiper resistance IW = 1mA, VCC = 5V IW = 1mA, VCC = 2.7V IW Wiper current (Note 5) Noise (Note 7) Resolution Absolute linearity (Note 1) Relative linearity (Note 2) RTOTAL temperature coefficient (Note 5) Ratiometric temperature coefficient (Notes 5, 6) CH/CL/CW (Note 5) VCC Potentiometer capacitances Supply Voltage See equivalent circuit X9317 X9317-2.7 4.5 2.7 -20 10/10/25 5.5 5.5 V(RH) = VCC, V(RL) = 0V -1 -0.2 300 +20 See test circuit Ref: 1kHz -4.4 -120 1 +1 +0.2 200 400 MIN -20 VSS TYP (Note 4) MAX +20 VCC 10 25 400 1000 +4.4 UNIT % V mW mW mA dBV % MI (Note 3) MI (Note 3) ppm/C ppm/C pF V V
DC Electrical Specifications
SYMBOL ICC1
VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated TEST CONDITIONS CS = VIL, U/D = VIL or VIH and INC = VIL/VIH @ min. tCYC RL, RH, RW not connected CS = VIH, U/D = VIL or VIH and INC = VIL or VIH. RL, RH, RW not connected CS VIH, U/D and INC = VIL RL, RH, RW not connected VIN = VSS to VCC -10 VCC x 0.7 -0.5 MIN TYP (Note 4) MAX 50 UNIT A
PARAMETER VCC active current (Increment)
ICC2 ISB ILI VIH VIL
VCC active current (Store) (non-volatile write) Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH voltage CS, INC, U/D input LOW voltage
400 1 +10 VCC + 0.5 VCC x 0.1
A A A V V
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X9317
DC Electrical Specifications
SYMBOL CIN (Note 5) VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated (Continued) TEST CONDITIONS VCC = 5V, VIN = VSS, TA = 25C, f = 1MHz MIN TYP (Note 4) MAX 10 UNIT pF
PARAMETER CS, INC, U/D input capacitance
Endurance and Data Retention VCC = 5V 10%, TA = Full Operating Temperature Range
PARAMETER Minimum endurance Data retention NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/99 + V(RL), with n from 0 to 99. 2. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) - MI)]/MI. 3. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/99. 4. Typical values are for TA = 25C and nominal supply voltage. 5. This parameter is not 100% tested. 6. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2) x 106], with T1 & T2 being 2 temperatures, and n from 0 to 99. 7. Measured with wiper at tap position 99, RL grounded, using test circuit. MIN 100,000 100 UNIT Data changes per bit Years
Test Circuit
Equivalent Circuit
RTOTAL RH CH Force Current CW 25pF 10pF RW CL 10pF RL
Test Point
RW
AC Conditions of Test
Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V
AC Electrical Specifications
SYMBOL tCl tlD (Note 5) tDI (Note 5) tlL tlH tlC tCPHS tCPHNS (Note 5) tIW CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period
VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated MIN 50 100 1 960 960 1 10 100 1 5 TYP (Note 4) MAX UNIT ns ns s ns ns s ms ns s
PARAMETER
INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE) INC to RW change
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FN8183.1 September 9, 2005
X9317
AC Electrical Specifications
SYMBOL tCYC tR, tF (Note 5) INC cycle time INC input rise and fall time VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated (Continued) MIN 2 500 5 0.2 5 50 10 TYP (Note 4) MAX UNIT s s s V/ms ms
PARAMETER
tPU (Note 5) Power up to wiper stable tR VCC (Note 5) tWR VCC power-up rate Store Cycle
Power Up and Down Requirements
The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until 1 millisecond after VCC reaches its final value. The VCC ramp
spec is always in effect. In order to prevent unwanted tap position changes, or an inadvertent store, bring the CS and INC high before or concurrently with the VCC pin on powerup.
AC Timing
CS tCYC tCI INC tIL tIH tIC tCPHS 90% 90% 10% tID tDI tF tR tCPHNS
U/D tIW RW MI (3)
Typical Performance Characteristics
0 -50 -100 PPM -150 -200 -250 -300 -350 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105115125 TEMPERATURE (C)
FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
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FN8183.1 September 9, 2005
X9317 Pin Descriptions
RH and RL The high (RH) and low (RL) terminals of the X9317 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 200. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9317 will be placed in the low power standby mode until the device is selected once again.
Pin Names
SYMBOL RH RW RL VSS VCC U/D INC CS High terminal Wiper terminal Low terminal Ground Supply voltage Up/Down control input Increment control input Chip select control input DESCRIPTION
Principles of Operation
There are three sections of the X9317: the control section, the nonvolatile memory, and the resistor array. The control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. Electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, RW. The wiper acts like its mechanical equivalent and does not move beyond the first or last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.
Pin Configuration
DIP/SOIC/MSOP
INC U/D RH VSS 1 2 3 4 X9317 8 7 6 5 VCC CS RL RW
TSSOP
CS VCC INC U/D 1 2 3 4 X9317 8 7 6 5 RL/VL RW/VW VSS RH/VH
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven bit counter. The output of this counter is decoded to select one of one hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH.
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FN8183.1 September 9, 2005
X9317
The system may select the X9317, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained.
Mode Selection
CS L L H H X L L L INC U/D H L X X X H L Wiper up Wiper down Store wiper position to nonvolatile memory Standby No store, return to standby Wiper Up (not recommended) Wiper Down (not recommended) MODE
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FN8183.1 September 9, 2005
X9317 Applications Information
Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VREF RH VREF
RW
RL I
Three terminal potentiometer; variable voltage divider
Two terminal variable resistor; variable current
Basic Circuits
Buffered Reference Voltage
R1 +V +5V RW VREF + LMC7101 VOUT +V RW X 100K +5V 100K + LMC7101 VOUT = VW/RW (a) (b) RW VO VS
Cascading Techniques
+V +V
Single Supply Inverting Amplifier
R1 R2 +5V
VO = (R2/R1)VS
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysteresis
VIN
317 R1
VO (REG)
R1 VS 100k -
R2 VS +5V VO
LT311A + VO
Iadj R2 10k 10k 10k
+ LMC7101
}
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
+5V
VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min)
(for additional circuits see AN115)
} R1
R2
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FN8183.1 September 9, 2005
X9317 Packaging Information
8-Lead Plastic Dual In-Line (DIP) Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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FN8183.1 September 9, 2005
X9317 Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S (SOIC)
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050"Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8183.1 September 9, 2005
X9317 Packaging Information
8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) (1.78) .031 (.80) .041 (1.05) See Detail "A" (0.42) (0.65) All Measurements Are Typical Seating Plane (4.16) (7.72)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8183.1 September 9, 2005
X9317 Packaging Information
M Package 8-Lead Miniature Small Outline Gull Wing Package Type MSOP
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.025" Typical 0.220"
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN8183.1 September 9, 2005

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